1. Field of the Invention
The present invention relates to a clock synchronous semiconductor memory device operating in synchronization with an externally applied clock signal, and more particularly to an arrangement for reducing current consumption in internal data read/write circuitry in the memory device.
2. Description of the Background Art
FIG. 1 schematically shows an overall arrangement of a conventional synchronous pipelined semiconductor memory device. Referring to FIG. 1, the memory device includes a memory array MA grouped into a plurality of (n+1) memory blocks B#0 through B#n each including a plurality of static type memory cells 13 arranged in rows and columns. Word lines 19 are disposed corresponding to respective rows of memory cells 13 and are connected to memory cells 13 on the corresponding rows. Bit line pairs 12 are disposed corresponding to respective columns of memory cells 13 and are connected to memory cells 13 on the corresponding columns. Word line 9 receives a word line drive signal WL at H (logical high) level when selected, and bit line pair 12 transmits complementary data signals BL and /BL.
The memory device further includes a mode register 6 receiving and latching external control signals, or a write mode designation signal ZWE at an input terminal 2 and a chip enable signal ZCE at an input terminal 3 in synchronization with an external clock signal CLK received at a clock input terminal 4, an address register 5 incorporating a multibit address signal Add received at address input terminals 1 in response to an output signal of mode register 6 and the clock signal CLK, a word line select decoder 8 decoding an internal (row) address signal received from address register 5 to select a word line 9 in memory array MA, and local read/write circuits LC# through LC#n provided for respective memory blocks B#0-B#n and reading or writing internal data from or to selected memory cells in corresponding memory blocks B#-B#n in response to an output signal of mode register 6 and an internal (block and column) address signal from address latch 5.
Local read/write circuit LC#i (i=0-n) includes a bit line select decoder 10 decoding the internal address signal to generate a column select signal CSL and a block select signal BSL, a bit line select transfer gates 11 provided for respective bit line pairs 12 to be made conductive in response to column select signal CSL, a sense amplifier 16 receiving and amplifying data signals on internal input/output line pair 15 when activated in response to block select signal BSL and the output signal from mode register, and a write driver 20 for producing internal complementary write data signals onto internal input/output line pair 15 in accordance with an internal write data WD when activated in response to block select signal BSL and the output signal (mode designation signal) of mode register 6.
Bit line select transfer gate 11 includes n channel MOS transistors provided for respective bit lines in a corresponding bit line pair 12. Thus, when a bit line pair is selected, the selected bit line pair is coupled to internal input/output line pair 15 through a bit line select transfer gate 1 made conductive in response to the column select signal CSL at H level.
The memory device further includes a bit line load 14 provided for each bit line pair 12 to clamp a bit line potential BL or /BL at L level upon data reading and to precharge the bit line potentials BL and /BL at H level of power supply voltage Vcc in a standby or non-selected state, a data register 17 provided in common to memory blocks B#0-B#n, for transferring received data in synchronization with the clock signal CLK, and an output buffer 18 receiving an internal read data for outputting to a data input/output terminal 19 when activated in response to an output signal from mode register 6.
Data register 17 receives internal read data RD from a selected sense amplifier (SA) 16 for outputting to output buffer 18 upon data reading and receives external write data at input/output terminal 19 for outputting to write driver 20.
When chip enable signal ZCE is made active to instruct that the memory device (chip) is selected, externally applied address signal Add at address input terminals 1 and write mode designation signal ZWE at control input terminal 2 are latched into address register 5 and mode register 6, respectively, at a rising edge of clock signal CLK. A part of the latched address signal, or X address signal is supplied to word line select decoder 8 to be decoded therein, and a corresponding word line 9 is elected. The remaining of the latched address signal is supplied to bit line select decoder 10 in each of local read/write circuits LC#0-LC#n, to be decoded therein, and a bit line select transfer gate 11 in a selected memory block is made conductive in response to column select signal, and a bit line pair 12 is selected in memory array MA. Thus, a memory cell 13 present at a crossing of the selected word line 9 and the selected bit line pair 12 is selected.
When write mode designation signal ZWE designates a data read mode of operation, data stored in a memory cell 13 connected to the selected word line is read out onto a corresponding bit line pair 12 which in turn is precharged to a predetermined potential by an associated bit line load, and the read out data on the selected bit line pair 12 is transferred to sense amplifier 16 through the conductive bit line select transfer gate 11 and internal input/output line pair 15 in the selected memory block. Sense amplifier 16 in the selected memory block is enabled in response to block select signal BSL and the data read operation mode instructing signal from mode register 6, to amplify the read out data for supplying to data register 17. Data register 17 latches the data received from sense amplifier 16 and transfers the latched data to output buffer 18 in synchronization with a next rising of clock signal CLK. Output buffer 18 is enabled in response to the output signal from mode register 6, to buffer the data received from data register 17 for outputting to input/output terminal 19.
When write mode designation signal ZWE designates a data write mode of operation, data register 17 latches an external write data received through data input/output terminal 19 at the timing of the rising edge of the clock signal CLK at which address signal Add and write mode designation signal ZWE are latched. Write driver 15 in the selected memory block designated by block select signal BSL is activated in response to the output signal from mode register 6, to produce complementary data signals in accordance with internal write data from data register 17 onto the internal input/output line pair 15. Since write driver 15 has a larger current driving ability than bit line load 14, the complementary data signals are written into the selected memory cell 13 through the selected bit line select transfer gate 11 and the associated bit line pair 12.
In the memory device, internal data is transferred by data register 17 in a pipelined manner in synchronization with clock signal.
In a non-pipelined SRAM (static random access memory) in which the data register 17 is not provided, an output of a selected sense amplifier 16 is directly transferred to data input/output terminal 19 in data reading operation, while data at the terminal 19 is directly transferred to a selected write driver 20 and then written into a selected memory cell 13 through a selected bit line select transfer gate 11 and an associated bit line pair 12 in data writing mode of operation. Thus, control of input/output of data by the external clock signal CLK is not required.
FIG. 2 shows a detailed configuration of memory peripheral circuitry in the memory device shown in FIG. 1.
Referring to FIG. 2, memory cell 13 includes an n channel MOS (insulated gate type) transistor (driver transistor) 13-3 having a drain connected to a node NA, a source connected to receive a ground potential GND and a gate connected to a node NB, an n channel MOS transistor (drive transistor) 13-4 having a drain connected to node NB, a source connected to receive the ground potential GND and a gate connected to node NA, an n channel MOS transistor (access transistor) 13-1 responsive to a word line drive signal WL on word line 9 to be conductive for connecting node NA to a bit line 12-1, an n channel MOS transistor (access transistor) 13-2 responsive to word line drive signal WL to be conductive to connect node NB to a bit line 12-2, a resistance element 13-5 of a high resistance connected between node NA and a power supply node Vcc (node and voltage thereof are denoted by same reference character), and a resistance element 13-6 of a high resistance connected between node NB and power supply node Vcc. Driver transistors 13-3 and 13-4 constitutes a flipflop, and data signals are stored at nodes NA and NB. Resistance elements 13-6 and 13-6 act as pull up elements.
Word line select decoder 8 includes a unit decoder 8a provided for each word line 9. Unit decoder 8a includes an NAND circuit 8-1 receiving X address signal bits Ax1-Axn, and an inverter 8-2 receiving and inverting an output signal of NAND circuit 8-1. When received X address signal bits Ax1-Axn are all at H level, NAND circuit 8-1 supplies an output signal at L level, and responsively inverter 8-2 supplies the word line drive signal WL at H level onto word line 9.
Bit line select decoder 10 includes a block decoder 10a receiving and decoding Z (block) address signal bits AYn-AYm to produce a block select signal BSL, and a unit column decoder 10b enabled in response to an inverted block select signal at H level to decode Y column address signal bits AY1-AYl received from address latch for producing a column select signal CSL.
Block decoder 10a is provided commonly to all unit column decoders 10b in a corresponding memory block, and includes an NAND circuit 10-1 receiving Z address signal bits AYn-AYm to produce the block select signal BSL, and inverter 10-3 receiving the block select signal BSL. When all Z address signal bits AYn-AYm are at H level, the memory block is selected, and block select signal BSL goes low.
Unit column decoder 10b is provided for each bit line pair 12, and includes an NAND circuit 10-2 receiving an output signal of inverter 10-3 and Y address signal bits AY1-AYl, and an inverter 10-4 receiving an output signal of NAND circuit 10-2 to produce the column select signal CSL. When block select signal BSL is at L level and all Y address signal bits AY1-AYl are at H level, the column select signal CSL goes high.
Bit line load 14 includes a p channel MOS transistor 14-1 connected between power supply node Vcc and bit line 12-1 and having a gate connected to a ground node, and a p channel MOS transistor 14-2 connected between power supply node and bit line 12-2 and having a gate connected to the ground node. MOS transistors 14-1 and 14-2 serve as load elements.
Sense amplifier 16 includes an inverter 16-1 receiving a read/write mode designation signal R/ZW from mode register 6, a NOR circuit 16-2 receiving an output signal of inverter 16-1 and block select signal BSL, and a current mirror type differential amplifier 16a activated in response to an output signal of NOR circuit 16-2 for differentially amplifying data signals on internal input/output lines 15-1 and 15-2. NOR circuit 16-2 supplies an output signal at H level when read/write mode designation signal R/ZW is at H level indicating a data read operation mode and block select signal BSL is in a selected state at L level.
Differential amplifier 16a includes an n channel MOS transistor 16-3 responsive to the output signal of NOR circuit 16-2 for conducting to form a current flowing path between the power supply node and the ground node, n channel MOS transistors 16-4 and 16-5 for comparing data signals on internal input/output lines 15-1 and 15-2, and p channel MOS transistors 16-6 and 16-7 constituting a current mirror circuit for supplying current flows to MOS transistors 16-4 and 16-5 from the power supply node Vcc.
MOS transistor 16-4 is connected between a node NC and MOS transistor 16-3 and has a gate connected to internal input/output line 15-1. MOS transistor 16-5 is connected between a node ND and MOS transistor 16-3 and has a gate connected to internal input/output line 15-2. MOS transistor 16-6 is connected between the power supply node Vcc and node NC and has a gate connected to node MOS transistor 16-7 is connected between the power supply node Vcc and node ND and has a gate connected to node ND. Internal read out data RD is generated at node ND, and complementary internal read out data/RD is generated at node NC.
Write driver 20 includes an inverter 20-1 receiving internal write data WD from data register 17, a NOR circuit 20-2 receiving block select signal BSL, an output signal of inverter 20-1 and read/write mode designation signal R/ZW, a NOR circuit 20-3 receiving the block select signal BSL, internal write data WD from data register 17 and read/write mode designation signal R/ZW, a three state inverter 20a enabled in response to the output signal of NOR circuit 16-2 to invert an output signal of NOR circuit 20-2 for transmission onto internal data input/output line 15-1, and a three state inverter 20b enabled in response to the output signal of NOR circuit 16-2 to invert an output signal of NOR circuit 20-3 for transmission onto internal data input/output line 15-2.
Three state inverter 20a includes a p channel MOS transistor 20-4 having a source coupled to power supply node Vcc and a gate connected to receive the output signal of NOR circuit 20-2, a p channel MOS transistor 20-5 having a source connected to a drain of MOS transistor 20-4, a gate connected to receive the output signal of NOR circuit 16-2 and a drain connected to internal data input/output line 15-1, and an n channel MOS transistor 20-8 having a drain connected to internal data input/output line 15-1, a gate connected to receive the output signal of NOR circuit 20-2 and a source connected to the ground node.
Three state inverter 20b includes a p channel MOS transistor 20-6 having a source connected to the power supply node and a gate connected to receive the output signal of NOR circuit 20-3, a p channel MOS transistor 20-7 having a source connected to a drain of MOS transistor 20-6, a gate connected to receive the output signal of NOR circuit 16-2 and a drain connected to internal data input/output line 15-2, and an n channel MOS transistor 20-9 having a drain connected to internal data input/output line 15-2, a gate connected to receive the output signal of NOR circuit 20-3 and a source connected to the ground node.
Now, an operation of the circuitry shown in FIG. 2 in reading data will be described with reference to an operation waveform diagram of FIG. 3.
Before time T0, chip enable signal ZCE is set up to L level, and address signal is set up to an address A. At time T0, clock signal CLK rises to H level, and address signal Add and write mode designation signal ZWE are incorporated and latched in the address registers and mode register 6, respectively, at the rising edge of clock signal CLK because hip enable signal ZCE is at L level indicating that the memory device is selected. The latched signals Add and ZWE in the registers 3 and 6 are maintained therein until application of next L level of chip enable signal ZCE (at time T0).
Write mode designation signal ZWE is set to H level at the rising edge of clock signal CLK (at time T0), and data read out operation mode is designated. Responsively, the read/write mode designation signal R/ZW from mode register 6 is brought to H level.
In address signal Add (A), address signal bits Ax1-Axn are applied to NAND circuit 8-1 of each unit decoder 8a in word line select decoder 8. When all address signal bits are at H level, NOT circuit (inverter) 8-2 generates an H level signal onto word line 9, and word line drive signal WL is raised to H level. Responsively, access transistors 13-1 and 13-2 in memory cell 13 turn on to connect the storage nodes NA and NB to bit lines 12-1 and 12-2, respectively. When memory cell stores an H level data, driver transistor 13-3 is in an off state, and node NA is supplied with (positive) electric charges through resistance element 13-5 and is at H level. Driver transistor 13-4 is in an on-state, and node NB is kept at L level through discharging by the conducting driver transistor 13-4.
Potentials on nodes NA and NB are transferred onto bit lines 12-1 and 12-2, and the potential on bit line 12-2 lowers a little from H level precharged by load MOS transistor 14-2 because load MOS transistor 14-2 supplies electric charges to bit line 12-2. Bit line 12-1 is maintained at H level of Vcc.
On the other hand, Z address signal bits AYm-AYn are applied to NAND circuit 10-1 in block decoder 10R, and Y address signal bits AY1-AYl are applied to NAND circuit 10-2 in column decoder 10b. When all the bits AY1-AYn are at H level, block select signal BSL goes low, and column select signal CSL goes high.
Bit line select transfer gate 11 is made conductive in response to column select signal at H level, to connect the bit lines 12-1 and 12-2 with internal data input/output lines 15-1 and 15-2. In a standby state or in a non-selected state with block select signal BSL at H level, NOR circuits 16-2, 20-2 and 20-3 each supply an L level signal, and inverters 20a and 20b are enabled to supply H level signals at power supply potential Vcc onto internal data input/output lines 15-1 and 15-2.
In the data reading operation, inverter 16-1 in sense amplifier 16 supplies an L level signal in response to the signal R/ZW at H level. Therefore, in the selected memory block, the block select signal BSL is at L level, and NOR circuit 162 supplies H level signal to the gates of p channel MOS transistors 20-5 and 20-7. NOR circuits 20-2 and 20-3 supply L level signals to the respective gates of n channel MOS transistors 20-8 and 20-9. Thus, inverters 20a and 20b are brought into output high impedance state.
When bit lines 12-1 and 12-2 are coupled to internal data input/output lines 15-1 and 15-2, the potentials IO and /IO on the lines 15-1 and 15-2 change in accordance with the bit line potentials BL and /BL.
In sense amplifier 16, the output signal of NOR circuit 16-2 is at H level, and MOS transistor 16-2 is turned on to activate differential amplifier 16a. The potential IO is higher than the potential /IO and MOS transistor 16-4 is in a stronger on-state than MOS transistor 16-5 is MOS transistors 16-6 and 16-7 constitute a current mirror circuit and supply current flows of the same magnitude when they are the same in size with each other. Current flowing through MOS transistor 16-5 is smaller than the current flowing through MOS transistor 16-4 and is mirrored by MOS transistors 16-7 and 16-6 to be supplied to MOS transistor 16-4 Thus, the potential /RD at node NC is made lower than the potential RD at node ND. As the current flowing through MOS transistor 16-4 increases, the current flowing through MOS transistor 16-5 decreases, and MOS transistors 16-6 and 16-7 approach off-state. Potential /RD is further decreased, or amplified, and then data signals /RD and RD are latched in data register 17. Data register 17 supplies the latch data signals RD and/RD as read out data Q and at a second rising edge of clock signal CLK at time T1.
At time T1, chip enable signal ZCE is set to L level at the rising edge of clock signal. Address signal Add designates an address A' which in turn is in another memory block, and word line drive signal WL on word line 9 goes low because word line select decoder 8 selects another word line. Block select signal BSL goes high, and NOR circuits 16-2, 20-2 and 20-3 supply H level signals, and the potentials BL, /BL and IO, /IO are precharged by NOT circuits 2a and 2b. In addition, the differential amplifier 16a is deactivated in response to block select signal BSL at H level, and potentials RD and /RD are raised to H level by MOS transistors 16-6 and 16-7. Then, column select signal CSL is made low, and bit line select transfer gate 11 is made non-conductive, and bit lines 12-1 and 12-2 are isolated from internal data input/output lines 15-1 and 15-2. This memory block returns to the standby state, and memory cell selection operation is performed in the other selected memory block.
Now, data writing operation will be described with reference to a waveform diagram of FIG. 4.
Similarly on the data reading operation, when chip enable signal ZCE is set low, address signal Add, write mode designation signal ZWE and external write data D are latched into address register 5, mode register 6 and data register 17, respectively, at the rising edge of clock signal CLK at time T0. If data of L is to be written into a selected memory cell, data of L level is latched in data register 17 and internal write data WD of H level is output from data register 17.
In the data writing operation mode, write mode designation signal ZWE is set at low level at the rising edge of clock signal CLK, and internal read/write mode designation signal R/ZW from mode register 6 is made low.
According to X address signal bits AX1-AXn, word line select driver 8 selects the word line 9, and word line drive signal WL on the selected word line 9 is raised to H level. Responsively, access transistors 13-1 and 13-2 are turned on to connect the storage nodes NA and NB to bit lines 12-1 and 12-2, respectively.
On the other hand, bit line select decoder 10 falls block select signal BSL to L level in accordance with Z address signal bits AYm-AYn, and then raises column select signal CSL to H level in accordance with block select signal BSL and Y address signal bits AY1-AYl.
Bit line select transfer gate 11 is made conductive to connect bit lines 12-1 and 12-2 to internal data input/output lines 15-1 and 15-2 in response to column select signal CSL at H level.
Internal read/write mode designation signal R/ZW is at L level, NOT circuit 16-1 supplies an H level signal, and NOR circuit 16-2 generates an output signal at L level to deactivate the differential amplifier 16a.
In write driver 20, NOT circuit 20-1 supplies an L level signal in response to internal write data WD at H level, NOR circuit 20-2 supplies an output signal at L level in response to the signal R/ZW at L level, the output signal at L level from NOT circuit 20-1 and block select signal BSL at L level, and NOR circuit 20-3 outputs a signal at H level in response to internal write data at H level.
In inverters 20a and 20b, p channel MOS transistors 20-5 and 20-7 are made conductive in response to the L level signal from NOR circuit 16-2, MOS transistors 20-4 and 20-9 are made conductive, and MOS transistors 20-6 and 20-8 are made non-conductive.
Thus, in potentials IO and /IO precharged at Vcc level in a standby on non-selected state, the potential IO is maintained at H level by MOS transistors 20-4 and 20-5, while the potential /IO is discharged to L level of GD ground level by MOS transistor 20-9.
When bit line select transfer gate 11 is made conductive in response to column select signal CSL, the potentials IO and /IO are transferred to bit lines 12-1 and 12-2, and bit line potentials BL and /BL change in accordance with the potentials IO and /IO. Since access transistors 13-1 and 13-2 are in conductive states in response to word line dive signal WL, bit line potentials BL and /BL are transferred to storage nodes NA and NB. More specifically, H level potential (/BL) is transferred to the node NB to turn on driver transistor 13-3, and L level potential (BL) is transferred to the node NA to turn off driver transistor 13-4, and L level data is stored in the selected memory cell.
When chip enable signal ZCE and write mode designation signal ZWE are made low at the next rising edge of clock signal CLK at time T1, data register 17 latches a new write data D' to generate a corresponding internal write data WD (at H level in FIG. 4). Address signal Add is also latched into address register 5, and address signal bits AXY1-AXn and AY1-AYn are generated. This newly applied address signal Add designates an address A' in another memory block, and this selected memory block is brought into non-selected state. That is, word line drive signal WL and column select signal CSL1 are turned to L level, and block select signal BSL is turned to H level. Bit line potentials BL and /BL are charges to H level at Vcc level by bit line load 14, and the input/output line potentials IO and /IO are charged to H level at Vcc level by the inverters 20a and 20b.
In another memory block designated by the address signal Add (A'), memory cell selection operation and data writing operation are performed.
As described above, in the synchronous memory including SRAM (static random access memory), data read or write can be performed in one clock cycle. External signals such as the address signal, the chip enable signal and the write mode designation signal are incorporated and latched at the rising edge of the clock signal, and there is no need for considering the skew of these external signals, and therefore for considering the timing margins of these signals. Thus, internal operation starting timing can be made faster.
However, at least one word line is always in the selected state as far as the memory device (chip) is in the selected or operable state. Under the chip selected (enabled) state, a current flows from bit line load 14 to the ground node through bit line pair 12 and memory cell (including driver transistor). A word line connects a plurality (one row) of memory cells, and the current flowing through memory cells becomes significantly large.
Sense amplifier 16 includes a current mirror type differential amplifier 16a, which in turn causes a current flow from the power supply node to the ground node through the current mirror stage and comparing MOS transistors when activated. Write driver 20 includes three state inverters 20a and 20b of CMOS configuration, and a current flows from bit line load 14, through bit line pair 12, internal data input/output line pair 15 and the conducting n channel MOS transistor in the inverter 20a or 20b supplying L level signal, to the ground node. One of sense amplifier 16 and write driver 20 is always activated as far as the memory device is set into the operable (enabled) state. These current flows are both nonnegligible in view of recent trend of reduction of current consumption of a memory device. Particularly, as the number of data bits is increased, the number of operating sense amplifiers or write drivers is increased, and the current consumption becomes greater accordingly.